wv3hg264m64eeu-d4 february 2006 rev. 2 advanced* 1 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs 1gb C 2x64mx64 ddr2 sdram unbuffered description the wv3hg264m64eeu is a 2x64mx64 double data rate ddr2 sdram high density so-dimm. this memory module consists of sixteen 64mx8 bit with 4 banks ddr2 synchronous drams in fbga packages, mounted on a 200-pin so-dimm fr4 substrate. * this product is under development, is not quali? ed or characterized and is subject to change or cancellation without notice. note: consult factory for availability of: ? vendor source control options ? industrial temperature option features 200-pin, dual in-line memory module (so-dimm) fast data transfer rates: pc2-6400*, pc2-5300*, pc2-4200 and pc2-3200 utilizes 800*, 667*, 533 and 400 mb/s ddr2 sdram components v cc = 1.8v 0.1v v ccspd = 1.7v to 3.6v jedec standard 1.8v i/o (sstl_18-compatible) differential data strobe (dqs, dqs#) option four-bit prefetch architecture dll to align dq and dqs transitions with ck multiple internal device banks for concurrent operation supports duplicate output strobe (rdqs/rdqs#) programmable cas# latency (cl): 3, 4, 5 and 6 adjustable data-output drive strength on-die termination (odt) posted cas# latency: 0, 1, 2, 3 and 4 serial presence detect (spd) with eeprom 64ms: 8,192 cycle refresh gold edge contacts dual rank rohs compliant jedec package option ? 200 pin (so-dimm) ? pcb C 30.00mm (1.181") typ. operating frequencies pc2-3200 pc2-4200 pc2-5300* pc2-6400* clock speed 200mhz 266mhz 333mhz 400mhz cl-t rcd -t rp 3-3-3 4-4-4 5-5-5 6-6-6 * consult factory for availability
wv3hg264m64eeu-d4 february 2006 rev. 2 advanced 2 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs pin configuration pin# symbol pin# symbol pin# symbol pin# symbol 1v ref 51 dqs2 101 a1 151 dq42 2v ss 52 dm2 102 a0 152 dq46 3v ss 53 v ss 103 v cc 153 dq43 4 dq4 54 v ss 104 v cc 154 dq47 5 dq0 55 dq18 105 a10/ap 155 v ss 6 dq5 56 dq22 106 ba1 156 v ss 7 dq1 57 dq19 107 ba0 157 dq48 8v ss 58 dq23 108 ras# 158 dq52 9v ss 59 v ss 109 we# 159 dq49 10 dm0 60 v ss 110 cs0# 160 dq53 11 dqs0# 61 dq24 111 v cc 161 v ss 12 v ss 62 dq28 112 v cc 162 v ss 13 dqs0 63 dq25 113 cas# 163 nc 14 dq6 64 dq29 114 odt0 164 ck1 15 v ss 65 v ss 115 cs1# 165 v ss 16 dq7 66 v ss 116 a13 166 ck1# 17 dq2 67 dm3 117 v cc 167 dqs6# 18 v ss 68 dqs3# 118 v cc 168 v ss 19 dq3 69 nc 119 odt1 169 dqs6 20 dq12 70 dqs3 120 nc 170 dm6 21 v ss 71 v ss 121 v ss 171 v ss 22 dq13 72 v ss 122 v ss 172 v ss 23 dq8 73 dq26 123 dq32 173 dq50 24 v ss 74 dq30 124 dq36 174 dq54 25 dq9 75 dq27 125 dq33 175 dq51 26 dm1 76 dq31 126 dq37 176 dq55 27 v ss 77 v ss 127 v ss 177 v ss 28 v ss 78 v ss 128 v ss 178 v ss 29 dqs1# 79 cke0 129 dqs4# 179 dq56 30 ck0 80 cke1 130 dm4 180 dq60 31 dqs1 81 v cc 131 dqs4 181 dq57 32 ck0# 82 v cc 132 v ss 182 dq61 33 v ss 83 nc 133 v ss 183 v ss 34 v ss 84 nc 134 dq38 184 v ss 35 dq10 85 nc 135 dq34 185 dm7 36 dq14 86 nc 136 dq39 186 dqs7# 37 dq11 87 v cc 137 dq35 187 v ss 38 dq15 88 v cc 138 v ss 188 dqs7 39 v ss 89 a12 139 v ss 189 dq58 40 v ss 90 a11 140 dq44 190 v ss 41 v ss 91 a9 141 dq40 191 dq59 42 v ss 92 a7 142 dq45 192 dq62 43 dq16 93 a8 143 dq41 193 v ss 44 dq20 94 a6 144 v ss 194 dq63 45 dq17 95 v cc 145 v ss 195 sda 46 dq21 96 v cc 146 dqs5# 196 v ss 47 v ss 97 a5 147 dm5 197 scl 48 v ss 98 a4 148 dqs5 198 sa0 49 dqs2# 99 a3 149 v ss 199 v ccspd 50 nc 100 a2 150 v ss 200 sa1 pin names pin name function ck0,ck1 clock inputs, positive line ck0#, ck1# clock inputs, negative line cke0, cke1 clock enables ras# row address strobe cas# column address strobe we# write enable cs0#, cs1# chip selects a0-a9, a11-a13 address inputs a10/ap address input/auto precharge ba0,ba1 sdram bank address odt0,odt1 on-die termination control scl serial presence detect (spd) clock input sda spd data input/output sa1,sa0 spd address dq0-dq63 data input/output dm0-dm7 data masks dqs0-dqs7 data strobes dqs0#-dqs7# data strobes complement v cc core and i/o power v ss ground v ref input/output reference v cc spd spd power nc spare pins, no connect
wv3hg264m64eeu-d4 february 2006 rev. 2 advanced 3 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs functional block diagram odt0 cke0 cs1# odt1 cke1 spd sa0 scl sda v ss ddr2 sdrams, spd v ref ddr2 sdrams ddr2 sdrams, v cc, v ccq and v ccl v cc v cc spd serial pd wp sa1 scl a0 a1 a2 a0 - a13 ras# ddr2 sdrams cas# ddr2 sdrams we# ddr2 sdrams ddr2 sdrams ba0 - ba1 ddr2 sdrams 5% 3 ohm + 5% ? cs0# dqs1 dqs1# dm1 cs0# dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs dqs# dm dqs0 dqs0# dm0 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 dqs dm dqs5 dqs5# dm5 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs dqs# dm dqs4 dqs4# dm4 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 dqs dm dqs3 dqs3# dm3 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs dqs# dm dqs2 dqs2# dm2 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 dqs dqs# dm dqs7 dqs7# dm7 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs dqs# dm dqs6 dqs6# dm6 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 dqs dqs# dm o d t 0 c k e 0 cs1# i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs dqs# dm i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 dqs dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs dqs# dm i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 dqs dqs# dm o d t 1 c k e 1 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs dqs# dm i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 dqs dm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs dqs# dm i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 dqs dqs# dm o d t 0 c k e 0 o d t 1 c k e 1 o d t 0 c k e 0 o d t 1 c k e 1 o d t 0 c k e 0 o d t 1 c k e 1 o d t 0 c k e 0 o d t 1 c k e 1 o d t 0 c k e 0 o d t 1 c k e 1 o d t 0 c k e 0 o d t 1 c k e 1 o d t 0 c k e 0 o d t 1 c k e 1 notes : 1. all resistor values are 22 ohms 5% unless otherwise specified 2. bax, ax, ras#, cas#, we# resistors : 3.0 ohms 5%. * wire per clock loading table/wiring diagrams * clock wiring clock input ddr2 sdrams *ck0/ck0# *ck1/ck1# 8 ddr2 sdrams 8 ddr2 sdrams 3 ohm cs0# cs1# cs0# dqs# dqs# cs1# dqs# dqs# cs0# cs1# cs0# cs1# cs0# cs1# cs0# cs1# cs0# cs1#
wv3hg264m64eeu-d4 february 2006 rev. 2 advanced 4 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs dc operating conditions all voltages referenced to v ss parameter symbol rating units notes min. type max. supply voltage v cc 1.7 1.8 1.9 v i/o reference voltage v ref 0.49 x v cc 0.50 x v cc 0.51 x v cc v1 i/o termination voltage v tt v ref -0.04 v ref v ref +0.04 v 2 notes: 1. v ref is expected to equal v cc/2 of the transmitting device and to track variations in the dc level of the same. peak-to-peak noise on v ref may not exceed +/-1percent of the dc value. peak-to-peak ac noise on v ref may not exceed +/-2 percent of v ref . this measurement is to be taken at the nearest v ref bypass capacitor. 2. v tt in sot applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref and must track variations in the dc level of v ref . absolute maximum ratings symbol parameter min max units v cc voltage on v cc pin relative to v ss -0.5 2.3 v v in , v out voltage on any pin relative to v ss -0.5 2.3 v t stg storage temperature -55 100 ?c i l input leakage current; any input 0v wv3hg264m64eeu-d4 february 2006 rev. 2 advanced 5 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs operating temperature condition parameter symbol rating units notes operating temperature toper 0 to 85 c 1, 2 notes: 1. operating temperature is the case surface temperature on the center/top side of the dram. for the measurement conditions, pl ease refer to jeded jesd51.2 2. at 0c - 85c, operation temperature range, all dram speci? cation will be supported. input dc logic level all voltages referenced to v ss parameter symbol min max units input high (logic 1) voltage v ih (dc) v ref + 0.125 v cc + 0.300 v input low (logic 0) voltage v il (dc) -0.300 v ref - 0.125 v input ac logic level all voltages referenced to v ss parameter symbol min max units input high (logic 1) voltage ddr2-400 & ddr2-533 v ih (dc) v ref + 0.250 - v input low (logic 1) voltage ddr2-667 v ih (dc) v ref + 0.200 - v input low (logic 0) voltage ddr2-400 & ddr2-533 v il (dc) - v ref - 0.250 v input low (logic 0) voltage ddr2-667, ddr2-800 tbd v il (dc) - v ref - 0.200 v
wv3hg264m64eeu-d4 february 2006 rev. 2 advanced 6 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs i cc specification symbol proposed conditions 806 665 534 403 units i cc0* operating one bank active-precharge; t ck = t ck (i cc ), t rc = t rc (i cc ), t ras = t ras min(i cc ); cke is high, cs# is high between valid commands; address bus inputs are switching; data bus inputs are switching tbd 744 704 704 ma i cc1* operating one bank active-read-precharge; i out = 0ma; bl = 4, cl = cl(i cc ), al = 0; t ck = t ck (i cc ), t rc = t rc (i cc ), t ras = t ras min(i cc ); cke is high, cs# is high between valid commands; address bus inputs are switching; data pattern is same as i cc 4w tbd 864 824 824 ma i cc2p** precharge power-down current; all banks idle; t ck = t ck (i cc ); cke is low; other control and address bus inputs are stable; data bus inputs are floating tbd 128 128 128 ma i cc2q** precharge quiet standby current; all banks idle; t ck = t ck (i cc ); cke is high, cs# is high; other control and address bus inputs are stable; data bus inputs are floating tbd 560 480 480 ma i cc2n** precharge standby current; all banks idle; t ck = t ck (i cc ); cke is high, cs# is high; other control and address bus inputs are stable; data bus inputs are switching tbd 640 560 560 ma i cc3p** active power-down current; all banks open; t ck = t ck (i cc ); cke is low; other control and address bus inputs are stable; data bus inputs are floating fast pdn exit mrs(12) = 0 tbd 480 480 480 ma slow pdn exit mrs(12) = 1 tbd 192 192 192 ma i cc3n** active standby current; all banks open; t ck = t ck (i cc ), t rc = t rc (i cc, t ras = t ras min(i cc ); cke is high, cs# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching tbd 880 800 800 ma i cc4w* operating burst write current; all banks open, continuous burst writes; bl = 4, cl = cl(i cc ), al = 0; t ck = t ck (i cc ), t ras = t ras max(i cc ), t rp = t rp (i cc ); cke is high, cs# is high between valid commands; address bus inputs are switching; data bus inputs are switching tbd 1184 1024 944 ma i cc4r* operating burst read current; all banks open, continuous burst reads, i out = 0ma; bl = 4, cl = cl(i cc ), al = 0; t ck = t ck (i cc ), t ras = t ras max(i cc ), t rp = t rp (i cc ); cke is high, cs# is high between valid commands; address bus inputs are switching; data pattern is same as i cc 4w tbd 1224 1064 944 ma i cc5** burst auto refresh current; t ck = t ck (i cc ); refresh command at every t rfc (i cc ) interval; cke is high, cs# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching tbd 2400 2240 2240 ma i cc6** self refresh current; ck and ck# at 0v; cke 0.2v; other control and address bus inputs are floating; data bus inputs are floating normal tbd 128 128 128 ma i cc7* operating bank interleave read current; all bank interleaving reads, i out = 0ma; bl = 4, cl = cl(i cc ), al = t rc d(i cc )-1*t ck (i cc ); t ck = t ck (i cc ), t rc = t rc (i cc ), t rrd = t rrd (i cc ), t rcd = 1*t ck (i cc ); cke is high, cs# is high between valid commands; address bus inputs are stable during deselects; data bus inputs are switching. tbd 1824 1824 1824 ma i cc speci? cation is based on samsung components. other dram manufactures speci? cation may be different. note: * value calculated as one module rank in this operating condition, and all other module ranks in icc2p (cke low) mode. ** value calculated re? ects all module ranks in this operating condition.
wv3hg264m64eeu-d4 february 2006 rev. 2 advanced 7 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs ac timing parameters & specifications ac characteristics 806 665 534 403 parameter symbol min max min max min max min max unit clock clock cycle time cl = 6 t ck (6) tbd tbd ps cl = 5 t ck (5) tbd tbd 3,000 8,000 ps cl = 4 t ck (4) tbd tbd 3,750 8,000 3,750 8,000 5,000 8,000 ps cl = 3 t ck (3) tbd tbd 5,000 8,000 5,000 8,000 5,000 8,000 ps ck high-level width t ch tbd tbd 0.45 0.55 0.45 0.55 0.45 0.55 t ck ck low-level width t cl tbd tbd 0.45 0.55 0.45 0.55 0.45 0.55 t ck half clock period t hp tbd tbd min (t ch , t cl ) min (t ch , t cl ) min (t ch , t cl ) ps clock jitter t j i t tbd tbd -125 125 -125 125 -125 125 ps data dq output access time from ck/ck# t ac tbd tbd -450 +450 -500 +500 -600 +600 ps data-out high-impedance window from ck/ck# t hz tbd tbd t ac max t ac max t ac max ps data-out low-impedance window from ck/ck# t lz tbd tbd t ac min t ac max t ac min t ac max t ac min t ac max ps dq and dm input setup time relative to dqs t ds tbd tbd 100 100 150 ps dq and dm input hold time relative to dqs t dh tbd tbd 225 225 275 ps dq and dm input pulse width (for each input) t d i pw tbd tbd 0.35 0.35 0.35 t ck data hold skew factor t qhs tbd tbd 340 400 450 ps dqdqs hold, dqs to ? rst dq to go nonvalid, per access t qh tbd tbd t hp - t qhs t hp - t qhs t hp - t qhs ps data valid output window (dvw) t dvw tbd tbd t qh - t dqsq t qh - t dqsq t qh - t dqsq ns data strobe dqs input high pulse width t dqsh tbd tbd 0.35 0.35 0.35 t ck dqs input low pulse width t dqsl tbd tbd 0.35 0.35 0.35 t ck dqs output access time from ck/ck# t dqsck tbd tbd -400 +400 -450 +450 -500 +500 ps dqs falling edge to ck rising setup time t dss tbd tbd 0.2 0.2 0.2 t ck dqs falling edge from ck rising hold time t dsh tbd tbd 0.2 0.2 0.2 t ck dqsdq skew, dqs to last dq valid, per group, per access t dqsq tbd tbd 240 300 350 ps dqs read preamble t rpre tbd tbd 0.9 1.1 0.9 1.1 0.9 1.1 t ck dqs read postamble t rpst tbd tbd 0.4 0.6 0.4 0.6 0.4 0.6 t ck dqs write preamble setup time t wpres tbd tbd 000p s dqs write preamble t wpre tbd tbd 0.35 0.35 0.35 t ck dqs write postamble t wpst tbd tbd 0.4 0.6 0.4 0.6 0.4 0.6 t ck write command to ? rst dqs latching transition t dqss tbd tbd wl - 0.25 wl + 0.25 wl - 0.25 wl + 0.25 wl - 0.25 wl + 0.25 t ck address and control input pulse width for each input t ipw tbd tbd 0.6 0.6 0.6 t ck address and control input setup time t is tbd tbd 200 250 350 ps address and control input hold time t ih tbd tbd 275 375 475 ps address and control input hold time t ccd tbd tbd 222t ck ac speci? cation is based on samsung components. other dram manufactures speci? cation may be different. continued on next page
wv3hg264m64eeu-d4 february 2006 rev. 2 advanced 8 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs ac timing parameters (cont'd) ac characteristics 800 665 534 403 parameter symbol min max min max min max min max unit command and address active to active (same bank) command t rc tbd tbd 55 60 65 ns active bank a to active bank b command t rrd tbd tbd 7.5 7.5 7.5 ns active to read or write delay t rcd tbd tbd 15 15 15 ns four bank activate period t faw tbd tbd 37.5 37.5 37.5 37.5 37.5 37.5 ns active to precharge command t ras tbd tbd 45 70,000 45 70,000 45 70,000 ns internal read to precharge command delay t rtp tbd tbd 7.5 7.5 7.5 ns write recovery time t wr tbd tbd 15 15 15 ns auto precharge write recovery + precharge time t dal tbd tbd t wr + t rp t wr + t rp t wr + t rp ns internal write to read command delay t wtr tbd tbd 7.5 7.5 10 ns precharge command period t rp tbd tbd 15 15 15 ns precharge all command period t rpa tbd tbd t rp+ t ck t rp+ t ck t rp+ t ck ns load mode command cycle time t mrd tbd tbd 222t ck cke low to ck,ck# uncertainty t delay tbd tbd t is + t ck + t ih t is + t ck + t ih t is + t ck + t ih ns self refresh refresh to active of refresh to refresh command internal t rfc tbd tbd 127.5 70,000 127.5 70,000 127.5 70,000 ns average periodic refresh interval t ref i tbd tbd 7.8 7.8 7.8 s exit self refresh to non-read command t xsnr tbd tbd t rfc (min) + 10 t rfc (min) + 10 t rfc (min) + 10 ns exit self refresh to read command t xsrd tbd tbd 200 200 200 t ck exit self refresh timing reference ti sxr tbd tbd t is t is t is ps odt odt turn-on delay t aond tbd tbd 222222t ck odt turn-on t aon tbd tbd t ac (min) t ac (max) + 1000 t ac (min) t ac (max) + 1000 t ac (min) t ac (max) + 1000 ps odt turn-off delay t aofd tbd tbd 2.5 2.5 2.5 2.5 2.5 2.5 t ck odt turn-off t aof tbd tbd t ac (min) t ac (max) + 600 t ac (min) t ac (max) + 600 t ac (min) t ac (max) + 600 ps odt turn-on (power-down mode) t aonpd tbd tbd t ac (min) + 2000 2 x t ck + t ac (max) + 1000 t ac (min) + 2000 2 x t ck + t ac (max) + 1000 t ac (min) + 2000 2 x t ck + t ac (max) + 1000 ps odt turn-off (power-down mode) t aofpd tbd tbd t ac (min) + 2000 2.5 x t ck + t ac (max) + 1000 t ac (min) + 2000 2.5 x t ck + t ac (max) + 1000 t ac (min) + 2000 2.5 x t ck + t ac (max) + 1000 ps odt to power-down entry latency t anpd tbd tbd 333t ck odt power-down exit latency t axpd tbd tbd 888t ck power-down exit active power-down to read command, mr[bit12=0] t xard tbd tbd 222t ck exit active power-down to read command, mr[bit12=1] t xards tbd tbd 7 - al 6 - al 6 - al t ck a exit precharge power-down to any non- read command. t xp tbd tbd 222t ck cke minimum high/low time t cke tbd tbd 333t ck ac speci? cation is based on samsung components. other dram manufactures speci? cation may be different.
wv3hg264m64eeu-d4 february 2006 rev. 2 advanced 9 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs 3.80 (0.150) max 1.10 (0.043) 0.90 (0.035) pin 1 67.75 (2.667) 67.45 (2.656) 20.00 (0.787) typ 1.80 (0.071) (2x) 0.60 (0.024) typ 0.45 (0.018) typ pin 199 pin 200 pin 2 2.15 (0.085) 6.00 (0.236) 63.60 (2.504) 2.55 (0.100) 1.00 (0.039) typ typ back view front view 30.15 (1.187) 29.85 (1.175) 47.40 (1.866) typ 11.40 (0.449) typ 4.2 (0.165) typ 4.10(0.161) (2x) 3.90(0.154) package dimensions for d4 ** all dimensions are in millimeters and (inches) ordering information for d4 part number clock/data rate speed cas latency t rcd t rp height** wv3hg264m64eeu806d4xg* 400mhz/800mb/s 6 6 6 30.00mm (1.181") typ wv3hg264m64eeu665d4xg* 333mhz/667mb/s 5 5 5 30.00mm (1.181") typ wv3hg264m64eeu534d4xg 266mhz/533mb/s 4 4 4 30.00mm (1.181") typ wv3hg264m64eeu403d4xg 200mhz/400mb/s 3 3 3 30.00mm (1.181") typ * consult factory for availability notes: ? rohs product. (g = rohs compliant) ? vendor speci? c part numbers are used to provide memory component source control. the place holder for this is shown as a l ower case "x" in the part numbers above and is to be replaced with respective vendors code. consult factory for quali? ed sourcing options. (m = micron, s = samsung & consult factory for others) ? consult factory for availability of industrial temperature (-40c to 85c) option
wv3hg264m64eeu-d4 february 2006 rev. 2 advanced 10 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs part numbering guide wv 3 h g 2 64m 64 e e u xxx d4 x g wedc memory (sdram) ddr 2 gold dual rank depth bus width component width x8 1.8v unbuffered speed (mb/s) package 200 pin component vendor name (m = micron) (s = samsung) g = rohs compliant
wv3hg264m64eeu-d4 february 2006 rev. 2 advanced 11 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs document title 1gb C 2x64mx64 ddr2 sdram unbuffered revision history rev # history release date status rev 0 created february 2005 advanced rev 1 1.1 updated ac speci? cations november 2005 advanced rev 2 2.1 update speci? cations ? v cc ? maximum rating febraury 2006 advanced
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